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Micron plans to use wafer bonding with its upcoming 1ε DRAM process, then adopt High-NA EUV lithography in later DRAM generations. It is also developing vertical HBM and vertical edge-inference memory for integration directly on processors; timelines and technical details remain unspecified.
Micron plans to use wafer bonding with its upcoming 1ε DRAM process and adopt High-NA EUV lithography for subsequent generations, according to a report by Tom’s Hardware. The plans outline how the company intends to keep advancing memory after removing 4F2 memory cells from its roadmap, while it also develops vertical memory products designed to sit directly on processors.
The reported strategy combines different manufacturing approaches rather than relying on the 4F2 cell design, which Micron has dropped from its roadmap. Micron is expected to introduce wafer bonding alongside 1ε DRAM, while High-NA EUV is planned for later process generations. The report does not specify when those later generations will arrive or which exact manufacturing steps would use the technology.
Micron is also working on two forms of processor-integrated memory: vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM). Both are described as being integrated directly on top of processors. That places the work beyond conventional DRAM scaling, although details such as capacity, performance, packaging, product availability and intended customers have not been provided.
The report frames these efforts against rival memory makers’ plans to use smaller DRAM transistors toward the end of the decade. It does not give a direct comparison of Micron’s proposed approach with competitors’ roadmaps, nor does it provide performance or manufacturing-cost estimates. The company’s plans should therefore be read as a development direction, not evidence that the technologies are already in production.
Memory roadmap · Development plans
How Micron Plans to Advance Next-Gen DRAM
Wafer bonding is planned alongside the upcoming 1ε process, with High-NA EUV intended for later generations. Micron is also developing vertical memory designed to sit directly on processors.
01 / The development
Three strands in the plan
The report describes process technology and processor integration as development directions. It does not establish production readiness or measurable gains.
Upcoming process
Wafer bonding
Planned alongside Micron’s 1ε DRAM process. The report gives no implementation details, schedule, or product linkage.
Later generations
High-NA EUV
Intended for subsequent DRAM generations. The first generation and the manufacturing steps that may use it are unspecified.
Processor integration
vHBM + vEIM
Vertical high-bandwidth memory and vertical edge-inference memory are being developed for placement directly on processors.
Micron has dropped this cell approach from its future plans.
Wafer bonding is reported alongside the upcoming process.
High-NA EUV is planned for subsequent generations.
vHBM and vEIM target direct processor integration.
02 / Two design paths
Scaling and integration
The approaches address related memory challenges, but the report does not say they share a process roadmap or will appear in the same products.
Advance manufacturing
Wafer bonding is associated with 1ε; High-NA EUV is reserved for later generations. Rivals are forecast to pursue smaller DRAM transistors toward the end of the decade, but no product-level comparison is supplied.
Place memory vertically
vHBM and vEIM are described as memory integrated directly on top of processors. Capacity, speed, power, packaging, target processors, and customers remain undisclosed.
These are reported development plans, not confirmation of shipping technology. The report provides no yield, cost, density, performance, prototype, or release data to quantify the expected impact.
03 / Roadmap visibility
Milestones to watch
The sequence is broad; specific dates and product milestones have not been announced in the report.
1ε with wafer bonding
Clarify timing, how bonding is applied, and whether manufacturing demonstrations or products follow.
High-NA EUV
Identify the first later DRAM generation and the specific steps expected to use the lithography approach.
04 / Key questions
What is known so far?
What is planned for 1ε?
Wafer bonding is planned alongside the upcoming process. The report does not specify its launch date or precise implementation.
When will High-NA EUV arrive?
It is planned for generations after 1ε. No first generation or adoption schedule is given.
What are vHBM and vEIM?
Vertical high-bandwidth memory and vertical edge-inference memory concepts intended for direct integration on processors.
Why pursue these approaches?
With 4F² cells dropped from its roadmap, Micron is pursuing other ways to advance DRAM. Their benefits are not yet quantified.
Micron’s Alternatives to Cell Shrinking
DRAM makers need ways to improve density and capability as memory generations advance. With 4F2 cells no longer on Micron’s roadmap, the reported plan points to other methods for maintaining progress: wafer bonding in an upcoming process and High-NA EUV in later generations. Whether these methods can keep Micron competitive will depend on implementation, yields, costs and performance—details not given in the report.
The processor-integrated concepts address a related but distinct need. vHBM and vEIM are being developed as memory that can be placed directly above processors, potentially supporting designs where memory placement and processor integration matter. No measured benefits or shipping products are identified, so their practical effect remains to be demonstrated.
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From 4F2 Cells to New Process Tools
Micron’s roadmap change matters because the company is not continuing with 4F2 memory cells as a route for future DRAM scaling. The reported alternative pairs wafer bonding with the upcoming 1ε process technology and reserves High-NA EUV for subsequent generations. The material does not explain how wafer bonding will be applied within 1ε or how the sequence relates to specific DRAM products.
High-NA EUV is a lithography approach intended for advanced chip manufacturing. In Micron’s reported plan, it is a future-generation tool rather than a feature specified for the upcoming 1ε process. Separately, vHBM and vEIM describe vertical memory concepts intended for direct processor integration. The report gives no launch schedule for either memory type and does not say whether they will use the same process roadmap.
The competitive backdrop is a forecast: rivals are planning to use smaller DRAM transistors toward the end of the decade. That is not a claim that those designs are already shipping. The available information does not identify particular rival products or establish a timetable against which Micron’s plans can be measured.
Schedules and Product Details Remain Open
The reported plans do not include production or release dates for wafer-bonded 1ε DRAM, High-NA EUV-based generations, vHBM or vEIM. They also provide no measurements for density, speed, power use, yield or cost, making it impossible to assess how much each approach may improve memory products.
It is not clear how Micron will implement wafer bonding, which later DRAM generation will first use High-NA EUV, or whether the two techniques will be combined in a particular product. The report also does not state whether the vertical memories have reached a working prototype, what processors they would pair with, or when they might be sold. Comparisons with rivals’ planned transistor scaling remain broad rather than product-specific.
Milestones to Watch in Micron’s Roadmap
The next useful indicators would be more detail on the 1ε process, including the role of wafer bonding and its expected timing, followed by a clearer schedule for High-NA EUV adoption. Public information on process demonstrations, manufacturing readiness or products could show whether the stated direction has advanced beyond development plans.
For vHBM and vEIM, further announcements would need to clarify their technical specifications, processor integration, intended uses and availability. Until Micron provides those details, the report establishes the company’s broad areas of work but not when customers can expect products or what measurable benefits they will deliver.
Source: Tom’s Hardware
Key Questions
What is Micron planning for its next DRAM process?
Micron plans to introduce wafer bonding with its upcoming 1ε DRAM process. The report does not specify the process’s launch date or explain the precise implementation.
When will Micron use High-NA EUV?
High-NA EUV is planned for DRAM generations after 1ε. No particular generation or schedule is given.
What are vHBM and vEIM?
They are memory types Micron is developing: vertical high-bandwidth memory and vertical edge-inference memory. The reported plan is to integrate them directly on top of processors, but specifications and availability are not stated.
Why is Micron pursuing these approaches?
Micron has removed 4F2 memory cells from its roadmap and is pursuing other ways to advance DRAM. The report describes wafer bonding and later High-NA EUV as parts of that approach, but does not quantify their expected benefits.
Source: Tom’s Hardware
